Computer monitoring system

ABSTRACT

A computer monitoring system connects into the channel, serving as a link between a CPU and peripheral devices. Channel signals are extracted in a channel interface module, altered to be compatible with the logic in a data collection module and sent to a data collection module along with event codes generated within the channel interface module to indicate certain sequences and/or combinations of signals occurring on the channel. The data collection module is programmable to select those peripheral devices it wants to monitor and the type of information to be collected.

BACKGROUND OF THE INVENTION

The present invention is in the field of computer performance monitoringequipment.

Computer performance monitoring has become an established industrywithin the much larger data processing industry. Performance monitoringis necessitated by the high costs of equipment, the large variety ofhardware and software, and the need to optimize the utilization of suchequipment. Broadly, monitoring equipment provides the user withinformation concerning the events taking place in computer equipment,when such events take place, and the frequency of such events. Bothhardware and software and combination hardware/software monitors arepresently in use. The hardware picks off signals from CPUs or peripheraldevices, notes the time of occurrence of such signals, stores thesignals and/or the time and/or the fact of the signal occurrence, andmay provide a visual output of such information to the user. Software isused principally to format the collected data in useful form for thecomputer user.

The standard monitors select the signals for monitoring by attaching aprobe to a line inside the CPU or peripheral device carrying the signalsto be measured. The probes consist of differential amplifiers whichpresent a high impedance to the line to which they are attached. Twosignificant problems with this standard method are lack of flexibilityand a substantial increase in probes necessary for collecting a largevariety of information. For example, once the probes are attached, thesignals measured are determined. To measure different signals, theprobes have to be removed and attached to other lines. Also, if it isdesired to measure activity in a CPU and in a plurality of peripheraldevices and collect such information, a substantial number of probeswould be required and it would be necessary to provide long wires fromthose probes attached to distant peripheral units.

Prior art monitors are the subject of several patents. Taylor, U.S. Pat.No. 3,399,298, provides direct connection to specific elements of thehost computer to be monitored. The monitor counts standard clock pulsesto provide an indication of a time period during which the specificelement is being checked. During that time period, a second counter isprovided with the same clock pulses but only during the moments whilethe element being monitored is active. Thus, the ratio of the two countsin the two counters indicates an efficiency measurement for theparticular device being monitored.

A patent of Martin, U.S. Pat. No. 3,906,454, is directed toward amonitor for a host computer. According to the Martin patent, the hostcomputer must be specially programmed or arranged to provide signalsthat indicate to the monitor that certain other signals should beaccummulated or otherwise processed for monitoring.

The Deese U.S. Pat. No. 3,818,458 departs from the technique of countingor timing individual signals received from various points in a computer,but does so by only monitoring certain specific computer statusindications and recording the time at which there is a change in one ofthese status indications.

Other standard monitoring systems or apparatus are taught by Freeman, etal., U.S. Pat. No. 3,763,474, Murphy, U.S. Pat. No. 3,540,003, Murphy,U.S. Pat. No. 3,522,597, Rash, et al., U.S. Pat. No. 3,588,837, andKandiew, U.S. Pat. No. 3,692,989.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a computerperformance monitor whih overcomes the above-mentioned problems.

According to the present invention, selection of items to be measured isnot predetermined by the placement of probes but is determined in themonitoring electronics and, consequently, can be altered electronically.Also, according to the present invention, measurement of peripheraldevice activity is accomplished without attaching probes directly to theperipheral devices.

These objects and advantages are obtained by connecting the monitoringhardware as if it were a peripheral device to a CPU channel by pickingoff signals on the channel, by monitoring combinations of signals andsequences of signals and generating event codes which identify thecombinations and sequences, by reducing the data picked off the channelin accordance with programmable instructions for each peripheral deviceon the channel, and collecting packets of information in dependence uponthe event code generated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a preferred embodiment of the presentinvention as connected with a host system.

FIG. 2 is a block diagram of a channel interface module according to apreferred embodiment of the present invention.

FIG. 3 is a block diagram of a data collection module according to apreferred embodiment of the present invention.

FIGS. 4 and 4a illustrate, in block diagram, the event translator ofFIG. 3.

FIG. 5 is a block diagram of the short busy detector of FIG. 2.

FIG. 6 is a block diagram of the system reset detector and the selectivereset detector of FIG. 2.

FIG. 7 is a block diagram of the FIFO and FIFO control apparatus of FIG.3.

FIG. 8 is a block diagram of the halt I/O detector of FIG. 2.

FIG. 9 is a block diagram of the initial select detector of FIG. 2.

FIG. 10 is a block diagram of the end procedure detector of FIG. 2.

FIG. 11 is a block diagram of the data buffer registers shown generallyin FIG. 3.

FIG. 12 is a block diagram of the command/status load selection meansand the command/status register shown generally in FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

A preferred embodiment of the invention will be described in theenvironment of monitoring the performance of an IBM 360 or 370 computersystem. However, it will be understood that the invention is applicableto other computer systems.

A CPU and peripheral device arrangement is shown in FIG. 1 and includesCPU 10, channel 11, channel bus 24, controllers 12-16, terminals12a-12f, printer 14a and disk drives 16a-16c. The nine peripheraldevices illustrated represent only a sampling of such devices that maybe connected to the channel bus 24. The devices shown are connected tothe CPU channel 11 via communication control 12, printer control 14 anddisk drive control 16 and via bus 24. As is well known, the channel buscarries addressing information, commands, status information, data, andflags or control signals back and forth. The particular arrangement andsequence of such signals on an IBM 360/370 channel is disclosed inseveral publications. For reference, see IBM Publication No. GA-22-6974,entitled "Channel to Control Unit OEM Information."

In general, each channel bus comprises thirty-nine (39) lines, ninelines carry a parallel eight-bit word plus parity out (from the CPU),nine carry a parallel eight-bit word plus parity in (to the CPU), twoare for address-in and address-out flags, respectively, one is forcommand-out flag, two are for service-in and service-out flags,respectively, two are for data-in and data-out flags, respectively, oneis for status-in flag, two are for OP-in and OP-out flags, respectively,and one is for the hold flag. The eighteen (18) lines carrying eight-bitbytes plus parity are referred to as the bus-in and bus-out lines. Thoselines carry address bytes, command bytes, status bytes and data bytes.

Although there are several sequences of signals on the channel, atypical sequence, designated as the Initial Select Sequence, is asfollows: the CPU sends an address byte on the bus-out lines, designatinga particular device, and raises the address-out flag; the device sendsits address on the bus-in lines and raises the address-in flag; the CPUsends a command byte on the bus-out lines and raises the command-outflag; the device sends a status byte on the bus-in lnes and raises thestatus-in flag; the device performs the command which may be to send orreceive multiple bytes of data on the bus-in or bus-out linesrespectively.

According to the present invention, the activity of the devices ismonitored by connecting directly to the channel bus a monitor consistingof a channel interface module (CIM) 18 and a data capture module (DCM)20. The monitor also preferably includes its own processing unit andmain memory, shown generally as a microcomputer 22, for collating thedata and presenting it to the user in any of the variety of typicalformats. The collation and data presentation, as well as the programmingof the microcomputer, does not constitute a feature of the inventionclaimed herein, and consequently, details of such a process will not beprovided. However, microcomputers are well known in the art, as ismonitoring software. Furthermore, given the arrangement of data collatedfor presentation by the DCM 20, anyone of ordinary skill in themonitoring and software arts would be able to program such a knownmicrocomputer to provide the desired collation and formatting of theinformation.

Among the typical devices that the invention can monitor arecommunications front ends such as the IBM 3705 and Comten 3670; unitrecord equipment, such as printers, card readers, etc.; and directaccess storage devices (DASD) similar to IMB's 3330 and 3350 massstorage devices. The type of information that can be gathered on thesethree classes of data processing equipment is described below.

As the importance of channel communications increases, performanceaccountability of this area becomes critical. The monitor can see everyevent on the channel. Consequently, the user can combine data in manyways to produce measurement data. The monitor can measure communicationsprocessing delays, or the time spent on a given transaction by the hostprocessor hardware and software, such as the amount of time between thetransaction first entering the host CPU via the channel and exiting thehost CPU by the same channel. The monitor also checks for sequences ofsignals or character strings. It can recognize character sequences offrom 1 to 255 characters in length. In addition to measuring messagelength, it can also measure message traffic, message direction (in orout of CPU) and message rate distribution. The monitor can measure andinterrogate data in a message to determine if transaction codes and keywords match user supplied transactions and key words. It is also able torecognize particular sequences of signals that are embedded in aparticular segment of the sequence.

Since everything on a channel bus is apparent to the monitor,unit/record events are particularly suited to be measured. Formerly,significant resources were required to measure unit/record events. But,as unit/record events process records one at a time, the monitor expendsminimum resources to obtain information which formerly was difficult toobtain. For example, such measurements as the following can now beroutine; number of cards read, number of cards per second (minute, hour,day, etc.), and number of lines (pages, characters, etc.) printed perpage (or unit of time). Even a measurement such as the identity of themost frequently printed character is routine.

The monitor can make DASD measurements, such as: contention analysis bydevice and control unit; rotational position sensing timings by device;reserve/release timings by device; seek timing, seek address and seekcounts by device; block size distributions; and device, control unit andchannel busy statistics.

The CIM 18 monitors all of the activity on the selector or blockmultiplexer channel, but does not in any way interact with it. The CIMitself preferably resides under the machine room floor where it isconnected directly into the channel cabling. The added resistance causedby the CIM should not exceed 2 ohms for any of the individual conductorsmaking up the cable harness. This must remain valid for cable lengthsapproaching six feet in length with two IBM compatible connectors, suchas the AMP models 86719-1 and 86719-2 attached to either end. Inaddition, the CIM must not draw more than 5 milliamps at a referencevoltage of 3.11 volts from any of the bus or tage lines. The CIM mustnot interfere with the channel operation so that repeated CIM powerinterruptions will have no effect on normal channel operation. The CIMcan be connected to the channel cables anywhere between the channelcontroller and the channel terminator.

The CIM performs the functions of detecting combinations and sequencesof flags on the channel and generating event codes identifying thecombinations and sequences, level changing and duration changing certainflags to levels and durations usable at the DCM, and multiplexing thebus-in and bus-out lines onto a single group of bus lines forpresentation to the DCM. It should be noted that the CIM collects andpasses on to the DCM all bytes on the bus lines--i.e., there is noselection or data sampling in the CIM.

The DCM receives the information presented to it by the CIM and operatesto either ignore the information, collect packets of information,excluding data, pertaining to a particular device, collect packets ofinformation plus a designated part of the data pertaining to a device,or collect packets of information plus disc drive CYLINDER, HEAD andSECTOR addresses when a seek or set sector command is involved. The DCMcontains a control word for each device address on the CPU channel. Thecontrol word is accessed when the DCM receives the device address. Thecontrol word commands the DCM either to ignore all informationpertaining to that device, to accept and form a packet of information,but no data, for that device, or to form the packet of information andcollect data beginning with byte x and ending with byte y of each datatransfer.

A block diagram of a CIM is illustrated in FIG. 2. It comprises aplurality of event detectors 50-60, an event code generator 68, a signallevel circuit 62, a data selector 64, a register 66 and a plurality oftransmit circuits 70a-70h. Each of the event detectors detects a signalstate change or a certain set of or sequence of conditions on thechannel and provides a TRUE or "1" output when the designated conditionsare satisfied. The six detectors provide a total of seven outputs, onlyone of which will be TRUE at any given time. The seven detector outputsare provided to an event generator 68 which provides a unique three-bitparallel output which identifies the TRUE input line and, therefore,identifies the event detected. For each event code generated, thegenertor 68 also raises the event code strobe.

The signal level circuit 62 receives eight channel flags, and, inresponse thereto, provides five output strobe pulses of proper level andduration for use in the DCM. The address-in, address-out, command-outand status-in flags result in the address, command and status strobes,respectively. The service-in, service-out, data-in and data-out flagsresult in the data strobes.

The data selector 64 receives the eight bus-in lines plus parity and theeight bus-out lines plus parity and multiplexes those lines onto eightbus lines and one parity line which are connected to a nine-bit register66. The transmit circuits 70A-70h transmit the designated codes, strobesand data to the DCM.

The short busy detector 60 is shown in detail in FIG. 5 and comprises asingle D flip-flop. The short busy flip-flop output becomes TRUE whenthe address-out flag is TRUE and status-in flag goes TRUE. The shortbusy event occurs when the controller for the peripheral device raisesthe status-in flag while the address-out flag is still up. This preventsan initial select sequence from progressing to completion.

Referring to FIG. 2, it is seen that the system reset detector 50 andthe selective reset detector 56 depend upon the OP-out and suppress-outflags. In actual operation, the false state of the OP-out flag isconnected to an enable input of event code generator 68, forcing alloutputs to zero. The lowest order bit of the output code is connected toan OR gate, the other input being the output resulting from a NANDconnection of OP-out and suppress-out. This is shown in FIG. 6. Thus, ifthe OP-out flag is false, there will be generated either a system resetevent code or a selective reset event code, depending upon the state ofthe suppress-out flag.

The halt I/O detector 54 is shown in detail in FIG. 8 and comprises aD-type flip-flop which is clocked when the hold-out flag goes FALSE, iscleared when the address-out goes FALSE, and has the OP-in applied toits D input. As long as the address-out flag is TRUE, the flip-flop canbe set to the state of the D input, which corresponds to the state ofthe OP-in flag whenever the hold-out flag goes FALSE.

The initial select detector 52 of FIG. 2 is shown in FIG. 9 comprising aD flip-flop and an OR gate with inverted output (i.e., a NOR gate). Theflip-flop is clocked to provide a TRUE or FALSE output corresponding tothe logic state of the hold-out input whenever address-out goes TRUE.The flip-flop is reset whenever service-out or power-up reset goes TRUE.

The end procedure detector 58 of FIG. 2 is shown in FIG. 10 ascomprising a pair of OR gates with inverted outputs and a D flip-flop.The flip-flop is clocked by status-in going TRUE to assume the statecorresponding to that applied to the D input. The latter is TRUE onlywhen address-out and initial select are FALSE. The flip-flop is reset byeither OP-in or power-up reset going TRUE.

A block diagram of the data collection module is illustrated in FIG. 3.The inputs are applied thereto from the CIM, and the data collected bythe DCM, which may be considered as the output data, is available to themicrocomputer. The inputs from the CIM are applied to a series ofreceivers 100-112. The bus lines, including nine bits in parallel, oneof which is the parity bit, are connected to the data receivers 100. Theinformation carried by the bus lines may be data, an address, a commandbyte or a status byte. The information applied to the data receiverappears at the output thereof and is applied to parity check apparatus116 and to data buffer registers 114. The parity check apparatus 116provides an output parity error indication whenever the parity isincorrect. The data buffer registers 114 comprise three sixteen-bitregisters arranged in six bytes. Consequently, the register holds sixbytes received by data receiver 100. The data buffer register hasapplied thereto several control signals which determine whether the datais entered into the registers 114, and, if so, whether it is thereafterentered into data memory 128 or applied directly to an output FIFO 152.The FIFO is a first-in, first-out buffer memory. The control inputs tothe data buffer registers 114 are data strobe, data window, seek, andset sector control lines. The data buffer registers 114 also receive anindication from a data byte counter 138 of the even/odd count of thedata bytes and indications of memory full and store cycle active fromthe memory control unit 134. The outputs are data and, in the case ofseek and set sector commands, address information, which are connectedto the data memory 128 and the input select 150 for the FIFO circuit152, respectively. A control output designated memory store request isapplied to the memory control 134 to initiate the writing of data intomemory 128.

Details of the data buffer registers 114 and associated logic are shownin FIG. 11 wherein the three register stages, each of which holds twobytes of data, are connected in cascade, with the data bytes on the busline out of receiver 100 (FIG. 3) connected to the even and odd bytesections of stage 1. The logic condition, shown in simplified logicform, for gating the bytes into the even and odd sections, respectively,are:

    DATA STROBE* EVEN NO. BYTE* (DATA WINDOW+SEEK+SET SECTOR); and

    DATA STROBE* ODD NO. BYTE* (DATA WINDOW+SEEK+SET SECTOR).

The EVEN NO. BYTE and its inverse are taken from the data byte counter138, which counts data bytes. The DATA STROBE is applied from eitherreceiver 102a or 102b via selector 102c. Thus, if there is a DATA WINDOWfrom the comparator and logic 140 and a DATA STROBE from selector 102c,an even-numbered byte will be gated into the top section of stage 1register 1102 and an odd-numbered byte will be gated into the bottomsection of stage 1 register 1102. Also, the presence of a SEEK or SETSECTOR command, as detected by command decoder 124, will result in theentry of bytes into stage 1 register 1102.

If stage 2 register 1104 is empty, the contents of stage 1 will betransferred to stage 2. If stage 3 register 1106 is empty and stage 2 isfull, the contents of the latter will be transferred to the former. Inthis manner, data always moves to the last stage of buffer registers114. The associated logic also provides an output control signal MEMORYSTORE REQUEST which is connected to the memory control 134 to intiatetransfer of data from stage 3 register 1106 to the memory 128. The logiccondition for generating a MEMORY STORE REQUEST is:

    [SEEK+SET SECTOR+MEMORY FULL]* [STAGE 3 FULL* STORE CYCLE ACTIVE+STAGE 2 FULL].

From the latter, it can be seen that the control signal will not begenerated in the case of a SEEK or SET SECTOR command. In the lattercases, the data in stage 3 (representing disc drive address information)will be inputted to the FIFO by other logic described subsequently.Also, the control signal will not be generated if the memory 128 isfull. Such a condition results in the generation of a MEMORY FULL signalas described hereafter. However, if there is neither a SEEK nor SETSECTOR command and the memory is not full, a MEMORY STORE REQUEST willbe generated if either stage 2 is full or if stage 3 is full and thememory is not currently writing in the contents of stage 3. The STOREACTIVE CYCLE from memory control 134 indicates that a storage cycle ispresently in progress. The memory control 134, in response to a storerequest, applies a write signal on the read/write line to data memory128 and, after the write is completed, increments the address in thewrite address register 130. The word (2 bytes) from the data bufferregister 114 is, therefore, written into the memory at a locationdefined by write address register 130.

The data collected in data memory 128 may be called for by themicrocomputer under the control of memory control 134 and read addressregister 132. The inputs from the microcomputer are not shown, forsimplicity, but such inputs would cause a signal to be applied to thememory control 134 and a read address to be applied to read addressregister 132. As a result, the data memory 128 would output the datalocated at the address indicated by the read address register 132. Also,as long as the memory control 134 continues to receive inputs from themicrocomputer, it would continue to increment the address in the readaddress register and output the data from the data memory 128. If themicrocomputer applies a specific read address to the register 132, theseries of data read from data memory 128 will be that beginning at thestorage location identified by the address entered into the read addressregister 132. Otherwise, the data memory 128 will simply output databeginning with the address just following the last read address. Thus,under normal circumstances, the data is both read from and written intothe memory locations in sequence.

A compare circuit 136 prevents input data from being written when thedata memory is full and thereby destroying stored data which has not yetbeen read out of the data memory 128. This is accomplished by applyingthe write address and read address to the compare circuit 136. When thetwo addresses are equal, a MEMORY FULL output is applied to the memorystore request circuit of unit 114 to inhibit further requests forwriting into the data memory 128 (see FIG. 11). The MEMORY FULL outputwill remain TRUE until further information is read out of data memory128, thereby resulting in a change of the read address 132.

As previously mentioned, the only data which gets into the data memory128 is that which is applied to the data buffer registers 114 during theexistence of the DATA WINDOW control signal. Generation of the lattercontrol signal is one of the features which permits datareduction--i.e., receipt of all of the data, but selction on only somuch of the data as the system is interested in. The apparatus forgenerating the DATA WINDOW will now be described. A receiver 104receives an ADDRESS STROBE from the CIM and applies that strobe to adevice address register 118. At the same time that an ADDRESS STROBE isreceived, the information on the input bus line will consist of theaddress of a device connected to the computer channel. That address onthe data line will pass through receiver 100 and be gated into thedevice address register 118 by means of the ADDRESS STROBE. The addressin the device address register 118 also addresses a control RAM 144which has a separate address location for each device address. As aresult, the control RAM 144 outputs a control word which is stored inthe address corresponding to the device address. The control wordsstored into control RAM 144 depend upon the system's interest in theparticular device whose address is in address register 118. The controlword has three fields, first byte count, last byte count and pseudoaddress. The pseudo address, like the input address, identifies theparticular device. However, the pseudo address corresponds to theaddress in the memory associated with the microcomputer, wherein all ofthe information about the device is collected. The field which isdesignated as the first byte count contains the number of the first byteof data which the system wants to collect. The field designated the lastbyte count contains a number representing the last byte of data whichthe systems wants to collect. For example, assume the addresscorresponding to a certain device arrives on the data lines 100 and isgated into the device address register 18 by the ADDRESS STROBE. Furtherassume that the control word for that particular device contains itspseudo address as well as a first byte count corresponding to 16 and alast byte count corresponding to 31. The pseudo address will beconnected directly through the input select means 150 to the FIFO 152.The numbers corresponding to the first and last bytes will be applied toa comparator 140. Following the address of the device, the device and/orthe CPU will begin putting data onto the channel. The data is picked upby the CIM and sent to the DCM on the bus lines. Also, each data word onthe channel will be accompanied by a DATA STROBE which is also picked upby the CIM and applied to the DCM. The DATA STROBE is applied toreceiver 102a or 102b and therethrough to a data byte counter 138. Thedata byte counter counts the bytes of data appearing on the channelduring the particular sequence described. The output from data bytecounter 138 is applied to comparator 140, wherein it is compared withthe first byte count and the last byte count. When the number in thedata byte counter equals the first byte count, the DATA WINDOW will goTRUE, and when the number in the data byte counter becomes greater thanthe last byte count, the DATA window will become FALSE. Consequently,the DATA WINDOW is TRUE for the duration that data between thedesignated first and last bytes are being applied to the data bufferregisters 114. In this way, the control word determines the specificportion of the input data which is to be collected. The remainder of theinput data is ignored.

In the case of certain devices, the system will not be interested in thedata. For those devices, the control word in the control RAM 144 willhave a first byte count field of one and a last byte count field ofzero. Simple logic in comparator 140 recognizes this condition andblocks generation of a DATA WINDOW. For certain other devices, thesystem will not want any information. For those devices, the controlword will have a first byte field with its most significant bit set toone and a last byte field with its most significant bit set to zero.This condition is also recognized by comparator 140. In this case, theDATA WINDOW will not be generated, but an output ADDRESS REJECT willbecome TRUE and will thereafter block storage of a packet of informationinto the FIFO 152. It is noted that the data byte counter is resetwhenever the COMMAND STROBE is TRUE. It is sufficient for the present tounderstand that the data byte counter will be reset during every initialselect sequence on the CPU channel.

The receivers 106 and 108 receive the COMMAND STROBE and STATUS STROBE,respectively. The COMMAND STROBE will occur whenever a command byteappears on the bus line, and a STATUS STROBE will appear whenever astatus byte appears on the bus line. The COMMAND and STATUS STROBES,following reception by receivers 106 and 108, respectively, are appliedto a command/status load selection means 120. The input from the datareceiver 100 is also connected to the command/status load selectionmeans 120. The function of the latter means is to decide whether thecommand byte or the status byte should be in the command/status register122 at the time the packet of information is collected by the FIFO 152.The load selection means 120 and register 122 operate broadly asfollows. Whenever a COMMAND STROBE is sensed, the load selection meansgates the command byte into the register 122. If a subsequent statusbyte is of the form OOOOXXOO, where X can be either one or zero, thisindicates that the sequence on the channel which has been commanded bythis CPU can take place. The load selection means 120, in this case,will not gate the status byte into the register 122. The command bytewill remain therein and be sent to the FIFO 152. On the other hand, ifthe status byte is of a form other than OOOOXXOO, this signifies thatthe commanded sequence cannot take place. In this case, the loadselection means 120 will gate the status byte into the register 122 toreplace the previously entered command byte. Also, the output linedesignated NOT INITIAL SELECT is generated internally and is TRUE whenthe status byte is not equal to OOOOXXOO.

A simple logic circuit for carrying out the logic of selection means 120and register 122 is shown in FIG. 12. A TRUE output from OR gate 1202commands the register 1214 to enter the eight-bit byte appearing on thebus line. This occurs under any of three conditions. First, if a COMMANDSTROBE is TRUE, the LOAD COMMAND becomes TRUE. Secondly, if the STATUSSTROBE is TRUE and the NOT INITIAL SELECT is TRUE, AND gate 1204 willprovide a TRUE input to OR gate 1202 to cause the LOAD COMMAND to beTRUE. Thirdly, if the STATUS STROBE is TRUE and any one or more of thestatus byte bits S7, S6, S3, S2, S1 and S0 is TRUE, the combination ofNOR 1206, invert 1208 and AND 1210 cause a TRUE LOAD COMMAND output. TheNOT INITIAL SELECT control line is the Q output of a D-type flip-flop121, whose clock input receives the STATUS STROBE and whose D input isTRUE when the status byte equals OOOOXXOO. Thus, when the status byte isnot equal to OOOOXXOO, the D input will be FALSE, and a simultaneouslyoccurring STATUS STROBE will cause the NOT INITIAL SELECT output to beTRUE. In general, this indicates that the monitored device will notcarry out the initial select sequence at this time.

The bus line, as well as the COMMAND STROBE, is also applied to acommand decoder 124, which functions to decode SEEK and SET SECTORcommands and to detect the read and write condition of all commands.Read or write is determined by the least significant bit of the commandbyte. If it is a one, the command relates to the writing of data fromthe channel to the control unit of the peripheral device. If it is azero, the command relates to the reading of data from the control unitto the channel. The read and write outputs from the command decoder areapplied to the selector 102c to cause selection of the data-in strobeand the data-out strobe, respectively.

In the CPU channel, the SEEK and SET SECTOR commands pertain to diskdrives, and they result in a unique but short sequence of informationoccurring on the bus lines of the channel. The unique information isaddress information, but it should be distinguished from address bytesoccurring along with the address flag. The latter bytes addressperipheral devices. The former, which are accompanied by a data flag,represent addresses internal to the disc drives. This information istreated as data by the monitor up to and including entry into the databuffer registers. When a SEEK or SET SECTOR command occurs, themonitoring system operates to bypass the data memory 128 and to directlyapply the address information in the buffer registers 114 to the FIFO152 for subsequent collection by the microcomputer. This is accomplishedby the command decoder 124 which receives the command words and providesa TRUE output on the SET SECTOR and SEEK output lines when the commandis a SET SECTOR and a SEEK command, respectively, The SET SECTOR andSEEK output lines are applied to the data buffer registers 114, asdescribed previously, to control the entry of the address informationinto the register 114.

A three-bit input event code is supplied to receiver 110 and gated intoan event translator 146 by an EVENT STROBE which passes through receiver112. In the specific embodiment described herein, there are seven inputevent codes representing seven events on the CPU channel. The inputevents and the respective event codes are:

    ______________________________________                                        System Reset       000                                                        Selective Reset    001                                                        Halt I/O           010                                                        Chained Initial Select                                                                           101                                                        Unchained Initial Select                                                                         100                                                        Short Busy         011                                                        Ending Procedure   110                                                        ______________________________________                                    

The event translator 146 operates to decode the incoming event code andprovide an output event code which depends in part upon the decodedinput event code and in part on the prior sequence of events. In orderto determine the prior sequence of events, the event translator 146 alsoreceives the following inputs: SEEK, SET SECTOR, NOT INITIAL SELECT,DATA RECEIVED AND LOST DATA. The input designated DATA RECEIVED isapplied from a data flip-flop 126 which is set by a DATA STROBE andreset whenever the ADDRESS STROBE goes TRUE. Consequently, the linedesignated data received will be TRUE, provided data has been receivedsubsequent to the last ADDRESS STROBE.

The input line designated LOST DATA is taken from simple logic, shownherein as being a part of memory control 134, which renders the LOSTDATA output TRUE when the MEMORY FULL output is TRUE, the data bufferregisters are full and a DATA STROBE occurs. The event translator 146also provides an output to the FIFO control means 156 to start loadingof the FIFO. It will be noted that the FIFO 152, which is a FIFOregister, stores information applied thereto in packets, each packetrepresenting a group of data pertaining to a particular device connectedto the CPU channel. The FIFO is shown as comprising an input selectportion 150 and a FIFO 152. The input select portion 152 selects theorder of information applied thereto for gating into the FIFO independence upon the output of DCM event code.

The information which is applied for entry into the FIFO consists of thefollowing:

(1) Pseudo Address--This information identifies the particular deviceabout which the information pertains, as well as identifying an addressin the microcomputer memory where all of the information is to becollected.

(2) Write Address--This information indicates the ending address plusone in data memory 128 where the data from the particular device isstored.

(3) Data Byte Count--This information, which is obtained from the databyte counter 138, indicates the number of bytes of data in the datarecord transferred on the CPU channel.

(4) Data Buffer Out--This information, which is directly obtained fromdata buffer registers 114, will only be applied to the FIFO when thereis a seek or set sector command. This information is the disc driveaddress information mentioned previously.

(5) Command/Status Word--This information designates the particularcommand being performed by the device or the status of the device whenthe command is not being carried out or an end or asynchronous statushas been presented by a device to the CPU channel.

(6) Output or DCM Event Code--This is the information from thetranslator 146 indicating the particular event taking place on the CPUchannel.

(7) Time Stamp--This is timing information from the timer 154 whichindicates the time at which the above information is applied to the FIFO152.

FIFO control means 156 is connected to an entry counter 158 which keepstrack of the loading of FIFO 152. The purpose of entry counter 158 is toprovide outputs indicating when the FIFO is empty, 75% full, andcompletely full. When the FIFO is 75% full, the designation indicatingthis fact is applied to a DCM status register 160. When the FIFO iscompletely full, meaning that the newest information applied theretowill have been lost, this designation is applied to the DCM statusregister 160. Other inputs applied to the DCM status register are LOSTDATA, PARITY ERROR from the parity check means 116 and a system resetfrom the CPU channel. The contents of the DCM status register 160, whichprovides an indication of the previously mentioned conditions, isavailable to the microcomputer. The DCM also includes a DCM address 148uniquely identifies the particular data collection module. The latteraddress is presented to the microcomputer along with the contents ofstatus register 160. The DCM address is particularly useful whenever aplurality of DCMs are connected to a single microcomputer.

The input event codes mentioned above are obtained from the CIM whichmonitors groups of signals on the CPU channel and provides the eventcodes corresponding to certain channel sequences. The particular channelsequences mentioned previously are standard sequences. The groups ofsignals occurring on the channel and the sequence of such signalscorresponding to those events may be found in several publications,including IBM Publication No. Ca-22-6974. For the purpose of providing abetter understanding of the present invention, but at the risk ofover-simplification, the significance of the above input sequence willbe briefly set forth.

The unchained initial select sequence begins with an address being sentout on the channel from the CPU to a device and is followed in series byan address-in on the channel, a command-out on the channel and astatus-in on the channel. The sequence designated chained initial selectis similar to the unchained initial selected sequence but it tells usthat the channel is maintaining communication with the particular deviceaddressed even after the first command has been carried out. In otherwords, this means that the previous command was for the same device. Thesystem reset sequence indicates that all of the peripheral devicesattached to the channel are being reset and the halt I/O sequenceindicates that the device presently selected for communication with theCPU is being instructed to effectively disconnect itself from thechannel. The selective reset sequence resets one of the devices. Theshort busy sequence occurs when an initial select is attempted but thecontrol unit or device addressed is busy. An ending procedure sequenceoccurs either at the end of transmission or is an asynchronous statusindicating that a non-selected device wants to communicate on the CPUchannel.

There are eleven output event codes from the event translator 146, andthey are:

    ______________________________________                                        System Reset           0000                                                   Asynchronous Status Following                                                                        0001                                                   A Seek Or Set Sector                                                          Asynchronous Status    0011                                                   Unchained Initial Select                                                                             0100                                                   Chained Initial Select 0110                                                   Short Busy/Aborted Initial Select                                                                    0010                                                   Selective Reset        1000                                                   Halt I/O               1010                                                   Ending Procedure       1110                                                   Ending Procedure With Lost Data                                                                      1111                                                   Ending Procedure Seek  1100                                                   Ending Procedure Set Sector                                                                          1101                                                   ______________________________________                                    

The event translator 146 of FIG. 3 is shown in greater detail in FIG. 4.As shown in FIG. 4, the input event code from the CIM is applied to anevent code holding register 502 and is clocked therein by the trueoutput from the Q terminal of a one-shot multivibrator 504, which istriggered by the event strobe. The event code held in register 502 isapplied to an event translator which translates the CIM event code intoa DCM or output event code, depending upon certain control signalsapplied thereto. The TRUE output at the Q terminal of one-shotmultivibrator 504 is also an output line from the event code translator146 designated event code received. The TRUE output from the Q terminalis ANDed with a FIFO NOT FULL line from the FIFO control 156 to providethe control output store into FIFO. This may be designated as the outputeven code strobe.

The inputs to the event translator 500, in addition to the CIM eventcode, are: data received, not initial select, lost data, seek and setsector. It should be noted that usually a control line and itsinverse--i.e., seek and not seek--are applied simultaneously to alllogic circuitry in the system. However, in order not to needdlesslyencumber the drawings and the explanation, often only one of the twocontrol lines is indicated.

The logic of the event code translator 500 is shown in detail in FIG. 4aas comprising a latching register 508 and a plurality of AND and ORgates connected as shown. The three bits of the CIM event code areclocked into catching register 508 which provides the CIM event codebits and the inverse thereof on its six output lines. The control inputsare applied as shown, and the four output lines represent the four-bitDCM event code.

Although the relationship between the three-bit CIM event codes and thefour-bit DCM event codes can be discerned by following the logic of FIG.4, the following explanation is offered to provide a betterunderstanding of that relationship.

Four of the CIM event codes result in four corresponding DCM eventcodes, respectively, independently of the status of the control inputlines. There are the events designated system reset, selective reset,halt I/O and short busy. For example, the CIM event code 001 (selectivereset) will result in the output event code 1000 (selective reset).

The CIM event codes initial select and initial select with chaining willresult in corresponding DCM event codes if the control line NOT INITIALSELECT is FALSE. However, if the latter control line is TRUE, each ofthe above CIM event codes will be translated into the DCM event code0010, which designates short busy or an aborted initial select.

The CIM event code end procedure (110) can be translated into any offive DCM event codes, depending on the state of several of the inputcontrol lines. If DATA RECEIVED is FALSE, and DCM event code will beasynchronous status (0011). If DATA RECEIVED is TRUE and one of SEEK,SET SECTOR or LOST DATA is TRUE, the DCM event code will be endprocedure seek (1100), end procedure set sector (1100) or end procedurewith lost data (1111), respectively. If DATA RECEIVED is TRUE and nne ofSEEK, SET SECTOR or LOST DATA is TRUE, the DCM event code will be endprocedure (1110).

Referring back to FIG. 3, the data entered into the FIFO 152 for eachpacket is arranged in groups of words. Each packet includes either twoor four words, with each word including two eight-bit bytes. A blockdiagram of the FIFO 152 and related apparatus--I.e., input select 152,control 156 and entry counter 158--is illustrated in FIG. 7. The eightbytes constituting the four words 0-3 of a packet are selected by FIFOdata selector 150, one byte at a time, in response to the selectoraddress.

Each of the lines, designated 0-15, applied to the FIFO data selector150 represents an eight-bit byte, the bits being in parallel. Theparticular byte selected to appear at the output depends on the four-bitselect address which is applied by the FIFO control means 156.

The relationship between the words 0-3, the input byte lines to selector150, the four-bit event code applied to the FIFO control 156 and theselector address will now be explained.

Words numbered 0 and 1 will be part of every packet irrespective of theoutout event code. The pseudo address, which consists of eight bits, isapplied on byte line 0 and makes up the first eight bits of word 0. Thecommand/status word, which consists of eight bits, is applied on byteline 1 and makes up the second eight bits of word 0. The four-bit outputevent code plus the first four bits of the twelve-bit time stamp isapplied via byte line 2 and makes up the first byte of word 1. The lasteight bits of the time stamp is applied via byte line 3 and makes up thesecond byte of word 1.

The above four byte always consitute the words 0 and 1 of the packet.When the output event code strobe goes TRUE, a counter in FIFO control156 begins counting, starting with a count 000 and applies same to theaddress input of selector 150. The count advances from 000 to 011,thereby causing selector 150 to sequentially apply the bytes on bytelines 0, 1, 2 and 3 to the selector output.

Subsequent activity depends upon the output event code and the status ofthe SEEK or SET SECTOR input. If the most significant bit of the outputevent code is 0, words 0 and 1 will be the only words included in thepacket of information. Thus, no further byte lines will be selected byselector 150. If the most significant bit is a 1, four words are to beincluded in the packet. Under the latter condition, which is easilydetected in FIFO control 156 by noting the status of the mostsignificant bit of the output event code, the counter will advance fourmore counts, starting with 100 and ending with 111. The selectoraddress, however, also depends on the status of SEEK or SET SECTOR. Ifthe latter is FALSE, the addresses applied to the selector 150 aresuccessively: 0100, 0101, 0110 and 0111. Thus, bytes on byte lines 3,4,5and 6 will be sequentially connected to the selector output toconstitute words 2 and 3 of the packet. If seek or SET SECTOR is TRUE,due to AND gate 1304, the successive addresses will be: 1100, 1101, 1110and 1111. The bytes on byte lines 12, 13, 14 and 15 will be successivelyselected.

The sixteen bits of the data byte counter 138 (FIG. 3) are applied tothe selector on byte lines 4 and 5. The sixteen-bit DCM memory addressfrom write address register 130 (FIG. 3) is applied to the selector onbyte lines 6 and 7. The seek or set sector address, constituting fourbytes obtained from data buffer registers 114 (FIG. 3), is applied viabyte lines 12-15.

The bytes from selector 150 are written into FIFO memory 1306, undercontrol of a write input from FIFO control 156, at an addresscorresponding to that in store address counter 1308. As the counter inFIFO control is advanced to place bytes on the selector 150 output line,the store address counter 1308 is advanced by a count of one and writeinput is applied to the memory 1306; also, a +1 is applied to entrycounter 158.

Whenever the holding registers 1312a and 1312b are empty, FIFO controlcauses bytes to be read out of FIFO memory 1306 and placed into theholding registers.

Whenever a packet is to be sent to the microcomputer for formatting andpresenting to the user, a request comes in to the FIFO control. Thiscauses the latter to present the holding register data to themicrocomputer and apply a read input to memory 1306 to read out the bytestored in the address held in read address counter 1310. Two successivebytes are read from memory 1306 and held in holding registers 1312a and1312b, respectively. The counter 1310 is advanced by a count of one foreach byte read from memory 1306. Also, each byte read results in a--1being applied to entry counter 158. The latter keeps track of the numberof bytes stored in memory 1306 and causes the output lines empty, 75%full and full to go true when those respective conditions exist inmemory 1306. The address selector 1314 selects a read or write addressdepending on whether a read or write operation is to be performed.

What is claimed is:
 1. A system for monitoring the performance ofperipheral devices connected to a central processing unit channel of thetype which carries data, addresses, commands, status information and aplurality of condition flags, comprising:a channel interface moduleconnected as a peripheral device to said channel, said channel interfacemodule comprising data selector means for receiving all said data,address, command and status information on said channel and providingsame on a bus line output thereof, a signal level circuit for receivingselected condition flags on said channel and providing condition strobesat an output thereof, and event means for receiving said condition flagsand providing input event codes representing selected sequences andcombinations of said condition flags; and a data collection moduleconnected to said channel interface module and receiving all informationon said bus line output, said condition strobes and said input eventcodes, said data collection module comprising a packet memory forstoring packets of information about selected peripheral deviceswhenever said selected peripheral devices are accessed on the channel, adata memory for storing selected portions of data passing between saidCPU and said selected peripheral device and appearing on said bus line,and means responsive to an address on said bus line for selectivelycontrolling the entry of information pertaining to the peripheral deviceidentifying by said address into said packet memory and for selecting aspecific part or none of the subsequent data appearing on said bus linefor storage in said data memory.
 2. A system as claimed in claim 1wherein said means responsive to an address comprises:control wordmemory means for providing a control word unique to each receivedaddress; first means responsive to said control word memory means fordetermining whether a packet of information pertaining to the peripheraldevice represented by said address should be collected; and second meansresponsive to said control word memory means for providing a gatingwindow to control the selection of data entered into said data memory.3. A system as claimed in claim 2 wherein said data collection modulefurther comprises means connected to said data memory and said packetmemory for providing as an input to said packet memory an address insaid data memory of data most recently entered therein.
 4. A system asclaimed in claim 3 wheren said data collection module further comprisesa data byte counter responsive to a strobe indicating the existence ofdata on the bus line for counting the number of data bytes on the busline, said data byte counter providing a count indication output as aninput to said packet memory.
 5. A system as claimed in claim 4 whereinsaid data collection module comprises command/status register means forstoring therein command and status words appearing on said bus line,said command/status register means providing its contents as an input tosaid packet memory.
 6. A system as claimed in claim 5 wherein said datacollection module further comprises a command/status register forstoring command and status words applied thereto and for providing itscontents as an input to said packet memory, command/status loadselection means responsive to those of said strobes indicating thepresence of command and status words on said bus line and responsive tosaid command and status words on said bus line for applying a saidcommand word when received to said command/status register and forreplacing the command word in said register with selected ones of saidstatus words.
 7. A system as claimed in claim 6 wherein said datacollection module comprises a buffer register connected between said busline and said data memory, said buffer register having an outputconnected as an input to said packet memory and as an input to said datamemory.
 8. A system as claimed in claim 7 wherein said data collectionmodule further comprises a command decoder responsive to command wordson said bus line for detecting the presence of a seek or set sectorcommand and for providing seek and set sector control signals, and logicmeans connected to said buffer register for entering information on saidbus line into said register, said information representing addressesinternal to selected ones of said peripheral devices, saidlast-mentioned address information being connected to said packet memoryas an output of said register.
 9. A system as claimed in claim 8 whereinsaid data collection module further comprises output event codegenerating means, responsive to said input event codes, a conditionsignal indicating the prior existence of data on said bus line, acondition signal indicating lost data preselected commands andpreselected status words, for providing an output event code uniquelyrelated to said words, condition signal and codes applied thereto, saidoutput event code being applied as an input to said packet memory, andinput selection means responsive to said output event code for selectingfrom the totality of inputs applied to said packet memory selected onesof said inputs for storage in said packet memory.
 10. A system asclaimed in claim 1 wherein said data collection module further comprisesmeans connected to said data memory and said packet memory for providingas an input to said packet memory an address in said data memory of datamost recently entered therein.
 11. A system as claimed in claim 1wherein said data collection module further comprises a data bytecounter responsive to a strobe indicating the existence of data on thebus line for counting the number of data bytes on the bus line, saiddata byte counter providing a count indication output as an input tosaid packet memory.
 12. A system as claimed in claim 1 wherein said datacollection module comprises command/status register means for storingtherein command and status words appearing on said bus line, saidcommand/status register means providing its contents as an input to saidpacket memory.
 13. A system as claimed in claim 1 wherein said datacollection module further comprises a command/status register forstoring command and status words applied thereto and for providing itscontents as an input to said packet memory, command/status loadselection means responsive to those of said strobes indicating thepresence of command and status words on said bus line and responsive tosaid command and status words on said bus line for applying a saidcommand word when received to said command/status register and forreplacing the command word in said register with selected ones of saidstatus words.
 14. A system as claimed in claim 1 wherein said datacollection module comprises a buffer register connected between said busline and said data memory, said buffer register having an outputconnected as an input to said packet memory and as an input to said datamemory.
 15. A system as claimed in claim 1 wherein said data collectionmodule further comprises output event code generating means, responsiveto said input event codes, a condition signal indicating the priorexistence of data on said bus line, a condition signal indicating lostdata preselected commands and preselected status words, for providing anoutput event code uniquely related to said words, condition strobe andcodes applied thereto, said output event code being applied as an inputto said packet memory, and input selection means responsive to saidoutput event code for selecting from the totality of inputs applied tosaid packet memory selected ones of said inputs for storage in saidpacket memory. .Iadd.
 16. A system for monitoring the performance ofperipheral devices connected to a central processing unit channel of thetype which carries data, addresses, commands, status information and aplurality of condition flags, comprising:a channel interface moduleconnected as a peripheral device to said channel, said channel interfacemodule comprising data selector means for receiving all said data,address, command and status information on said channel and providingsame on a bus line output thereof, a signal level circuit for receivingselected condition flags on said channel and providing condition strobesat an output thereof, an event means for receiving said condition flagsand providing input event codes representing selected sequences andcombinations of said condition flags; and a data collection moduleconnected to said channel interface module and receiving all informationon said bus line output, said condition strobes and said input eventcodes, said data collection module comprising a packet memory forstoring packets of information about selected peripheral deviceswhenever said selected peripheral devices are accessed on the channel,and means responsive to an address on said bus line for selectivelycontrolling the entry of information pertaining to the peripheral deviceidentified by said address into said packet memory. .Iaddend. .Iadd. 17.A system as claimed in claim 16, wherein said data collection modulefurther comprises a data byte counter responsive to a strobe indicatingthe existence of data on the bus line for counting the number of databytes on the bus line, said data byte counter providing a countindication output as an input to said packet memory. .Iaddend..Iadd. 18.A system as claimed in claim 16, wherein said data collection modulecomprises command/status register means for storing therein command andstatus words appearing on said bus line, said command/status registermeans providing its contents as an input to said packet memory..Iaddend..Iadd.
 19. A system as claimed in claim 16, wherein said datacollection module further comprises a command/status register forstoring command and status words applied thereto and for providing itscontents as an input to said packet memory, command/status loadselection means responsive to those of said strobes indicating thepresence of command and status words on said bus line and responsive tosaid command and status words on said bus line for applying a saidcommand word when received to said command/status register and forreplacing the command word in said register with selected ones of saidstatus words. .Iaddend..Iadd.
 20. A system as claimed in claim 16,wherein said data collection module further comprises output event codegenerating means, responsive to said input event codes, a conditionsignal indicating the prior existence of data on said bus line, acondition signal indicating lost data preselected commands andpreselected status words, for providing an output event code uniquelyrelated to said words, condition strobe and codes applied thereto, saidoutput event code being applied as an input to said packet memory, aninput selection means responsive to said output event code for selectingfrom the totality of inputs applied to said packet memory selected onesof said inputs for storage in said packet memory. .Iaddend..Iadd.
 21. Asystem as claimed in claim 16, wherein said data collection modulefurther comprises event translating means for processing said inputevent codes and for generating an output event code, input select meansfor receiving said output event code and for selecting the order ofinformation applied to said packet memory in response thereto, saidpacket memory comprising a first-in, first-out buffer memory means..Iaddend..Iadd.
 22. A system as claimed in claim 21, wherein said datacollection module further comprises means for controlling loading ofsaid first-in, first-out buffer memory means, said loading controllingmeans being operable in response to a signal received from said eventtranslating means; and means for indicating the amount of utilization ofsaid first-in, first-out buffer memory means. .Iaddend. .Iadd.
 23. Asystem as claimed in claim 16 wherein said means responsive to anaddress comprises, control word memory means for providing a controlword unique to each received address, and first means responsive to saidcontrol word memory means for determining whether a packet ofinformation pertaining to the peripheral device represented by saidaddress should be collective.